Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for opening a one-side contact region of a vertical transistor and a method for fabricating a one-side junction region using the same.
As mobile devices are widely spread and digital home appliances become smaller in size, the degree of integration of semiconductor memory devices constituting the mobile devices or the digital home appliances is rapidly increasing. Particularly, in the case of a DRAM device or a flash memory device, various attempts are being made to store a larger quantity of information in a limited space. In general, a DRAM device is configured with a transistor and a capacitor and has a stack structure in which the transistor is formed on a silicon semiconductor substrate and the capacitor is formed on the transistor.
For electrical connection between the transistor and the capacitor, a storage node contact is formed between a source region of the transistor and a lower electrode of the capacitor. In addition, a drain region of the transistor is electrically connected to a bit line through a bit line contact. In the structure in which the capacitor is formed on the planar type transistor, films for signal transmission (for example, a word line and a bit line) are formed between the transistor and the capacitor. Hence, it is difficult to ensure a space for increasing the capacity of the capacitor due to the space occupied by the films. Moreover, as a gate width of the planar type transistor becomes narrow to less than 40 nm, a larger amount of power may be consumed and an amount of a body current, which is a leakage current between the source region and the drain region of the transistor, may abruptly increase. In this regard, research into a vertical transistor is being actively conducted.
FIG. 1 is a view explaining the basic concept of a vertical transistor. As illustrated in FIG. 1, the vertical transistor 100 has a structure in which a drain region 112 is formed at one side of the lower portion of a semiconductor substrate 110, and a source region 114 is formed at one side of the upper portion of the semiconductor substrate 110. A channel region 116 is formed between the drain region 112 and the source region 114 in a vertical direction, and a gate dielectric film 118 and a gate electrode 120 are sequentially formed on the channel region 116, that is, the lateral side of the semiconductor substrate 110. When the vertical transistor 100 is applied to a DRAM device, a bit line is coupled to the drain region 112 and a storage node is coupled to the source region 114. Since the bit line is formed to be buried in the side of the lower portion of the semiconductor substrate 110, the space in which the storage node is to be formed is not reduced. Thus, the reduction of data storage capacity may be suppressed in spite of high integration. In addition, as the bit line is formed in a buried shape, bit line parasitic capacitance is reduced and thus the height of the storage node can be reduced by about ½ to ⅓.
However, in order to form the vertical transistor as described above, the drain region 112 may be formed at the one side of the lower portion of the semiconductor substrate 110. To this end, one side of the lower portion of the semiconductor substrate 110 at which the drain region 112 is to be formed, that is, the one-side contact region is opened. Although various methods for opening the one-side contact region and the method for fabricating the one-side junction region using the same have been proposed, they are composed of complicated steps and, in particular, much time is taken to perform the overall processes.